Virtual (VILT) Training Schedule 2016 XILINX VIRTUAL TRAINING COURSE DAYS JAN FEB MAR APR MAY JUN JUL AUG SEP OCT NOV DEC Designing with VHDL 5 - - - 4-8 - - 4-8 - - 3-7 - - Designing with Verilog 5 - - - - 9-13 - - - - - 14-18 - Designing with 7 Series Family 4 11-14 - 29-31 - - 13-17 - - 19-13 - - - Zynq Smarter Solutions – Hardware Workshop 2 - - 8-9 - - 7-8 - - 20-21 - 17-18 - Zynq Smarter Solutions – Software Workshop 2 - - - 12-13 - - 5-6 - - 11-12 - - Zynq: Introduction to Zynq EPP Architecture 2 - - - - 25-26 - - - 27-28 - - - Zynq: Embedded Systems Design (hardware) 4 25-28 - 15-18 - - 7-10 - - 6-9 - 8-11 - Zynq: Advanced Features of Embedded Systems Design (Hardware) 4 - 15-18 22-25 - - 14-17 - - 19-22 - 21-24 - Zynq: Embedded Systems Software Design 4 - - - 5-8 - 21-24 5-7 - - 3-6 - 13-16 Zynq: Advanced Features of Embedded Systems Software Design 2 - 22-23 - 13-14 - - 18-19 - - 18-19 - 20-21 Vivado: Essentials of FPGA Design 4 - 2-5 1-4 26-29 - 6-9 - - 12-15 - 14-17 - Vivado: Vivado Design Suite Static Timing Analysis and Design Constraints 5 - 8-12 7-11 - 2-6 20-24 - - 26-30 - 21-25 -
