Featuring AMD’s Designing with the Versal Adaptive SoC: Hardware Debug

This FREE online workshop will introduce the tools and techniques available to debug AMD Versal™ devices. Attendees will learn about features for debugging the fabric (programmable logic) and the available hard blocks. The workshop also introduce ChipScoPy APIs, which provide the Python interface to program and debug the Versal devices.
Starting from the Versal device design flow all debug features for programmable logic (PL) and hard block debugging will be enumerated then will be described how debug the Versal device using different debug IP cores and how to use the ChipScoPy APIs for hardware debugging.

After completing this Workshop attendees will have the necessary skills to:

▪ Describe the different tool flows for Versal devices
▪ Identify the debug interfaces in the Versal devices
▪ Utilize different debug IP cores, such as the AXIS ILA and AXIS VIO cores
▪ Identify the different hard block debugging tools
▪ Describe the Versal device debugging techniques for JTAG low-speed debug and high-speed debug port (HSDP) debug
▪ Utilize ChipScoPy APIs for hardware debugging