The MW_AES core performs the digital baseband function that can be used to protect electronic data…
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The MW_TS_MUX core is designed to multiplexer different transport stream and produce a single TS stream output. It is composed by MW_MUX_IN core that operate in conjunction with the MW_MUX_OUT core. The first core handles a single MUX input port and performs the pre-processing operations necessary for the MW_MUX_OUT core to correctly generate an output TS stream. Mux_in builds the database of the contents available in the TS, filters incoming programs, dropping unwanted PIDs, forwards the selected PIDs either to a bandwidth estimator, and performs the first stage of a PCR re-stamping process. Mux_out merges all incoming data streams, inject informational packets, enforces the TS output flow bit rate, injects Null locally generated, and performs the second stage of a PCR re-stamping process. The behaviour must be configured using an embedded MicroBlaze processor. Between the processor and the core an AXI interface is available, but also a PLB interface to be compliant with older design.
Family | Device | Slices | SliceReg | LUTs | DSP48E1 | BRAM | Speed(MHz) |
---|---|---|---|---|---|---|---|
Artix®-7 | XC7A200T | 3135 | 6008 | 6200 | 0 | 10 | — |
Zynq | Z-7020 | 3135 | 6008 | 6200 | 0 | 10 | — |
The core, delivered as is, is warranted against defects for two years from the date of purchase. Sixty days of phone and email technical support are included, starting from the delivery date.
The core has been verified through extensive simulation and physical implementation with Vivado® Design Suite on Xilinx Artix™ 7 and Zynq-7000 technology.
Deliverables
The following deliverables are available:
Optional deliverables:
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