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MW_DAB Modulator Core


General Description

The MW_DAB modulator core performs the digital baseband function for the transmission side of new generation Digital Audio Broadcasting. The MW_DAB core is designed to achieve high performance for a single chip FPGA based design, including control and status management.                  The modulator core is configurable to supports all several TX modes, 1/2/3/4. It receives as input the MPEG II audio signal and other data, as the information relating to FIB and Channel, and implements the modules to build the DAB modulated signal. Each service is individually coded at source level in the modulator, with error protection and time interleaving. The services are multiplexed in the Main Service Channel (MSC), and finally, Orthogonal Frequency Division Multiplexing (OFDM) is applied to the stream. Internal 20-bit architecture for high level MER and BER performances is provided.       The core is implemented to accept up to 16 channels as inputs. A larger capability could be obtained using additional FPGA resources. FPGA netlist only or complete design environment package are deliverable. The core was developed in Vivado tool, written in HDL code.


  • Fully compliant with ETSI EN 300 401 V1.4.1 2006-06, for DAB
  • DAB-Modes: I, II, III, IV
  • All protection levels supported
  • Synchronous design
  • Supported channels up to 16
  • Max delay < 100 ms, and depending on used DAB-Mode
  • Frequency range : VHF (III) 170 MHz to 254 MHz,   L band, with occupied bandwidth 1.536 MHz
  • Network type: SFN
  • Reference Standard : ITU-T G703-G704, EN 300401, EN 300799, EN 302077-2
  • DAB Input Signal : ETI (NI) 2.048 MHz or ETI (NA)
  • Typical MER > 40 dB at overall frequency range
  • Optional Features:
    • Digital linear adaptive pre-correction
    • Digital nonlinear adaptive pre-correction

Typical Application


Performance and Resource Utilization

Family Device Slices SliceReg LUTs DSP48E1 BRAM Speed(MHz)
Artix®-7 XC7A200T 12836 23540 47833 30 171 64
Zynq Z-7020 12836 23540 47833 30 171 64

Download Product Datasheet



The core, delivered as is, is warranted against defects for two years from the date of purchase. Sixty days of phone and email technical support are included, starting from the delivery date.


The core has been verified through extensive simulation and physical implementation with Vivado® Design Suite on Xilinx Artix™ 7 and Zynq-7000 technology.


The following deliverables are available:

  • FPGA netlist and Xilinx ISE or Vivado® Design Suite constraint files
  • User guide
  • Block level design document
  • VHDL test bench and test vectors

Optional deliverables:

  • Fully synthesizable VHDL source code
  • Synthesis script for XST
  • tcl script for Vivado® Design Suite

Available configuration

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