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General Description

The MW_DVB_FEC core performs the digital baseband function Forward Error Correction (FEC) for the transmission side of new generation Digital Video Broadcasting system. The FEC core implements the BCH/LDPC functions as defined by ETSI EN 302 755 and by ETSI EN 302 307; t-error correction BCH code shall be applied to each frame to generate an error protected packet; this shall be systematically encoded with LDPC before bit interleaving. The FEC core supports short and long FEC blocks, 16,200 bits and 64,800 bits, as defined by the standard. It support all code rate also for both short and normal frame. The core is designed to achieve high performance for a single chip FPGA based design, including control and status management. The core was developed in Vivado tool, written in HDL code. Rate, frame size can be changed frame by frame independently. Structural simulation and hardware test was performed to check compliant with DVB-T2 Verification & Validation Working Group reference, used their reference stream input and to compare encoded FEC frame after LDPC. FPGA netlist only or complete design environment package are deliverable.


  • Compliant with ETSI EN 302 755 V1.3.1 2011-11, for DVBT2, and ETSI EN 302 307 V1.2.1 2009-08, for DVBS2
  • FEC length : short 16,200 bits, and long 64,800 bits
  • Code Rate : 1/4, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6
  • Synchronous design using single clock
  • Low complexity design
  • Independently configuration frame by frame
  • Very fast FEC block encoded output, 16,223 clock cycles for short frame and 64,823 clock cycles for normal frame
  • Very high troughput, near real time
  • Small resource utilization

Typical Application


Performance and Resource Utilization

Family Device Slices SliceReg LUTs DSP48E1 BRAM Speed(MHz)
Artix®-7 XC7A200T 910 1910 2860 0 19 114
Zynq Z-7020 910 1910 2860 0 19 114

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The core, delivered as is, is warranted against defects for two years from the date of purchase. Sixty days of phone and email technical support are included, starting from the delivery date.


The core has been verified through extensive simulation and physical implementation with Vivado® Design Suite on Xilinx Artix™ 7 and Zynq-7000 technology.


The following deliverables are available:

  • FPGA netlist and Xilinx ISE or Vivado® Design Suite constraint files
  • User guide
  • Block level design document
  • VHDL test bench and test vectors

Optional deliverables:

  • Fully synthesizable VHDL source code
  • Synthesis script for XST
  • tcl script for Vivado® Design Suite

Available configuration

Core P/N Functionality
MW_DVBT2_FEC core DVBT2 FEC bch+ldpc
MW_DVBS2_FEC core DVBS2 FEC bch+ldpc

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