The MW_ATSC modulator core performs the digital baseband function for the transmission side of new generation Digital Video Broadcasting in the United States. It implements the framing functions as defined by A/53: ATSC Digital Television Standard, Parts 1-6, 2007. The MW_ATSC core is designed to achieve high performance for a single chip FPGA based design, including control and status management. 8VSB is used as the terrestrial transmission format. The modulator using eight discrete amplitude modulation levels, that are assigned eight different symbol values, to convey the MPEG compressed transport stream. It supports a payload data rate of 19.39 Mb/s in a 6 MHz channel. The input to the transmission subsystem from the transport subsystem is a data stream comprised of 188 byte MPEG-2. Internal 20-bit architecture for high level MER and BER performances is provided. A larger capability could be obtained using additional FPGA resources. FPGA netlist only or complete design environment package are deliverable. The core was developed in Vivado tool, written in HDL code.
- Fully compliant with A/53: ATSC Digital Television Standard, Parts 1-6, 2007
- 8 VSB transmission
- RS/Trellis encoder
- Segment/Field Sync and Pilot insertion
- Synchronous design
- AD9747 interface available, with interpolation stages
- Typical MER > 43 dB at overall frequency range
- Single Frequency Network Option
- Optional Features:
- Digital linear adaptive pre-correction
- Digital nonlinear adaptive pre-correction
- Spartan 6, Zynq/Artix7 technology and ISE Xilinx 14.7/Vivado tool
Performance and Resource Utilization
The core, delivered as is, is warranted against defects for two years from the date of purchase. Sixty days of phone and email technical support are included, starting from the delivery date.
The core has been verified through extensive simulation and physical implementation with Vivado® Design Suite on Xilinx Artix™ 7 and Zynq-7000 technology.
The following deliverables are available:
- FPGA netlist and Xilinx ISE or Vivado® Design Suite constraint files
- User guide
- Block level design document
- VHDL test bench and test vectors
- Fully synthesizable VHDL source code
- Synthesis script for XST
- tcl script for Vivado® Design Suite