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Italy Training Schedule

Italy Training Schedule 2016
XILINX TRAINING COURSE DAYS JAN FEB MAR APR MAY JUN JUL AUG SEP OCT NOV DEC
Designing with VHDL 3 11-13 - - 4-6 - - 27-29 - - 5-7 - -
Designing with Verilog 3 - - - - 2-4 - - - 5-7 - - -
Designing with 7 Series Family 2 14-15 22-23 - - - 13-14 - - 29-30 - 2-3 -
Designing with the UltraScale Architecture 2 18-19 - - - - 15-16 - - - - - 1-2
UltraScale Architecture Workshop 1 - 5 10 19 23 28 - - - - 2 -
Zynq Smarter Solutions – Hardware Workshop 1 - - - 1 3 29 - - 2 - 4 -
Zynq Smarter Solutions – Software Workshop 1 - - - 4 5 30 - - - 4 - -
Zynq: Introduction to Zynq EPP Architecture 1 - - 11 5/20 6/24 - 4 - 5 3 7 -
Zynq: Embedded Systems Design (hardware) 2 19-20 15-16 14-15 21-22 26-27 - 5-6 - 6-7 4-5 8-9 -
Zynq: Advanced Features of Embedded Systems Design (Hardware) 2 - 18-19 17-18 26-27 30-31 - 7-8 - 8-9 6-7 10-11 -
Zynq: Introduction to Zynq EPP Architecture 1 - - - - - - 25 - 26 24 14 -
Zynq: Embedded Systems Software Design 2 21-22 24-25 22-23 28-29 - 7-8 26-27 - 27-28 25-26 15-16 -
Zynq: Advanced Features of Embedded Systems Software Design 1 - 26 24 - - 9 28 - 29 27 17 -
Vivado: Essentials of FPGA Design 2 25-26 8-9 29-30 - 9-10 6-7 11-12 - 19-20 17-18 - 12-13
Vivado: Vivado Design Suite Static Timing Analysis and Design Constraints 3 27-29 10-12 - 5-7 11-13 8-10 13-15 - 21-23 19-21 - 14-16
Vivado: Debugging Techniques Using the Vivado Logic Analyzer 1 - - 9 18 20 27 18 - 29 27 - 19
Vivado: Advanced Tools & Techniques of Vivado Design Suite 2 - - 7-8 14-15 17-18 23-24 20-21 - 27-28 25-26 24-25 -
Signal Integrity and Board Design for Xilinx FPGAs 3 27-29 10-12 2-4 11-13 11-13 7-9 - - 21-23 - 21-23 -
How to Design a High-Speed Memory Interface 2 - - - 18-19 - - - - 21-22 - - -
C-based design: High-Level Synthesis with Vivado HLS 2 - - - - 23-24 - - - 19-20 - - -
DSP Design Using System Generator 2 - - 21-22 - - - 4-5 - - - 28-29 -