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EMBEDDED DESIGN COURSES
Zynq ultrascale+ mpsoc for the hardware designer

This course provides hardware designers with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family from a hardware architectural perspective. The emphasis is on Identifying the key elements of the application processing unit, (APU) and real-time processing unit (RPU), Reviewing the various power domains and their control structure, Illustrating the processing system (PS) and programmable logic (PL) connectivity, Utilizing QEMU to emulate hardware behavior.

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