Learn how to employ serial transceivers in UltraScale™ FPGA designs. The focus is on Identifying and using the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection, Utilizing the UltraScale FPGAs Transceiver Wizard to instantiate transceiver primitives, Synthesizing ...
This workshop introduces you to fundamental connectivity concepts and techniques for implementation in Xilinx FPGAs. The focus is on fundamental aspects of serial transceivers, PCIe® technology, memory interfaces, and Ethernet MACs. Design examples and labs show components from the Connectivity Targeted Reference Design (TRD). In addition, an IBERT lab is ...
Learn how to implement a Xilinx PCI Express® core in custom applications to improve time to market with the PCIe® core design. The focus is on Constructing a Xilinx PCI Express system within the customer education reference design, Enumerating various Xilinx PCI Express core products, Identifying the advanced capabilities of ...
Learn how to employ serial transceivers in your 7 series FPGA design. The focus is on Identifying and using the features of the serial transceiver blocks such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection, Utilizing the 7 Series FPGAs Transceiver Wizard to instantiate transceiver primitives, ...
Become acquainted with the various solutions that Xilinx offers for Ethernet connectivity. The course covers Learning the basics of the Ethernet standard, protocol, and OSI model, Performing simulation to understand fundamental principles, Assessing hardware design considerations and software development requirements, Becoming familiar with Ethernet IP core design architectures, core IP ...
Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components. This comprehensive course combines design technique and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.
This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using 7 series FPGAs. Additionally, you will learn about the tools available for high-speed ...
This course focuses on the fundamentals of the PCI Express® protocol specification. The typical PCIe® architecture, including data space, data movement, and the most commonly used Transaction Layer Packets (TLPs) are covered. Interrupts and error handling are also discussed. Implementation issues are covered in the two-day Designing a LogiCORE PCI ...