MW_FSIM Modulator Core

General Description

The MW_FSIM modulator core performs the physical layer for Return Link Asynchronous Access of the transmission side of a Satellite system. F-SIM asynchronous access is intended for access to interactive messaging services, with a single transport channel called Random Access Channel (RACH), and two physical channel called Physical Data Channel (PDCH) and Physical Control Channel (PCCH). PDCH is used to carry the RACH data burst, and the PCCH is used to carry physical layer signalling information; both channels are I/Q code multiplexed to form an Up-Link Burst (ULB), with a preamble followed by PDCH/PCCH. Six different possible sizes of the RACH data burst length are supported (in total bits), namely 960, 1920, 3600, 7200, 14400 and 36000 bits, and three allowed symbols rate are present, called chip rate, 1920, 3840 and 7680 kchip/s. Depending on the effective size of the RACH data burst length and of the size of the CRC, rate matching will be performed after FEC encoding (Turbo-coder 1/3). To be remarked that to cope with the FEC interleaving size limitation of 5114 bits, large burst lengths are obtained concatenating consecutive FEC frames. After interleaving and mapping, a channelization operation, with OVSF code, transforms every symbol into a number of chips, and then a scrambling code is used to spread signal, the same scrambling solution as foreseen in 3GPP WCDMA. F-SIM modulator core was developed in Vivado tool, written in HDL code, and tested on Xilinx Artix™ 7 series and Xilinx Zynq™ FPGA. Rate, frame size, OVSF code, scrambling and other parameters can be changed frame by frame independently. Structural simulation and hardware test was performed to check compliant with Matlab model. Return Link Encapsulation core can be included also. FPGA netlist only or complete design environment package are deliverable.

Support

The core, delivered as is, is warranted against defects for two years from the date of purchase. Sixty days of phone and email technical support are included, starting from the delivery date.

Deliverables

The following deliverables are available:

• FPGA netlist and Xilinx ISE or Vivado® Design Suite constraint files
• User guide
• Block level design document
• VHDL test bench and test vectors

Optional deliverables:

• Fully synthesizable VHDL source code
• Synthesis script for XST
• tcl script for Vivado® Design Suite